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Command to Store, Restore a RTL Compiler session
Are there commands similar to synopsys's save_session and load_session in RTL Compiler.
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Scan mode and scan chain control from internal registers
Hi, I have unique requirement that scan mode be set by internal register which would control output at PO. By default PI/PO which drives scan are set for something else. Before scan starts, I need to...
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How do I delete clock groups (created via set_clock_groups)
Hi,I have been using set_false_paths between clocks, and found out that it is better to use clock groups using set_clock_groups. Therefore, I updated my SDC files, but I now have a slight issue. I use...
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Two warnings(external_delay and CSA rejected)
There are two kind of warnings always happened during synthesis. I checked them in the user manual but I do not know how to solve them. 1. The following primary outputs have no clocked external...
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Exclude Paramter name/value during module generation in LEC
Hi, I'm using Conformal LEC to match RTL vs Netlist (synopsys's DC generated). Our requirement is just to use Uniquification numbers for same modules, and do not require tool to append parameter...
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How to use the Encounter RTL Compiler Super-Thread with Tivoli Workload...
Hello all, Please I would like to use my Encounter RTL Compiler, later the EDI, to place the parallel synthesis into a HPC cluster. I understand that for this purpose I must use Super-Thread, and that...
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cell_leakage_power
Does Encounter use default "cell_leakage_power" in the library cell for calculating leakage, or does it use the state-dependent leakage power provided in .lib?
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finding average,dynamic, static power
I have design the full adder with different style in virtuoso(cadence). I want to find the power consumption of the same. I have downloaded some manual in which different methods are given to find...
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set_false_path -through and set_load on the output ports
If i have set false paths through all the output ports and also specified a specific load on the output ports, will rccompiler/encounter optimize these paths to meet the DRV's that arise because of the...
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using ModelSim/QuestaSim VCD file in RTL compiler
Hi,I want to use VCD file from QuestaSim 6.0 in RTL compiler to obtain power report. The netlist file I am using in QuestaSim for simulation and VCD file generation is also generated by RTL compiler...
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Creating a reset scan test using Encounter Test
Has anyone seen this problem? I have been trying to create a script for running Encounter Test using TCL. In the script I wrote the line:create_reset_tests WORKDIR=directory TESTMODE=FULLSCAN...
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RTL compiler to minimize area
Hello all, I am using RTL compiler to synthesize a pure combiniational digital designs. I would like to know how to constraints the synthesis tool to minimize the Area as its first periority or even...
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Asynchronous FIFO design
Hi, I am new to logic design and trying to design an Asynchronous FIFO. can somebody suggest some good docs to read? regards,abhinavpr
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how to compare designware like DW02_multp with LEC
hi everyone,Our design instantced a lot designware and we always compare these designware with their behavior model when run FV with LEC. This method always works, only except DW02_multp and some other...
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RTL compiler command for retaining design hierarchy
Hi,Is there a command in RTL compiler which can force the synthesizer to retain original hierarchy of the design, like there is in Xilinx ISE for instance? Thanks.
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How to avoid unwanted removal of logic during synthesis
Hi All,I am synthesizing a processor design with RTL compiler. The synthesized netlist works fine and contains all necessary logic when I set a loose clock constraint (5000ps). But when I synthesized...
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how to add synthesizable delay in design
I am trying to add a delay of 3ns and 5 ns in my design but it not synthesizable in RC-compilor..anyone have idea how to add a synthesizable deslay in verilog........
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power differences after post-syn using VCD
Hi,I want to get a quick look at the power consumption of one block. --use RTL Compiler generate netlist(after syn) and sdf--run gate sim with or without sdf annotated, get VCD--use netlist and VCD in...
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Does clock power included in Power Report ?
Hi All,I am conserned whether my power reports include clock power or I have to calculate it separately. Currently I am defining clock period using "define_clock" command before loading my Netlist and...
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