Hi,
I have been using set_false_paths between clocks, and found out that it is better to use clock groups using set_clock_groups. Therefore, I updated my SDC files, but I now have a slight issue.
I use RTL compiler to do some sanity checks of SDC prior to handoff. In pseudo code
read netlsit
for sdc in func1.sdc func2.sdc scan.sdc loop
reset_design
read_sdc
timing lint, timing reports etc
write_sdc -strict
endloop
Previously, this has worked well, but it seems that clock_groups cannot be deleted. In the above, reset_design leaves the clock groups untouched, therefore my exported SDC files have clock groups for clocks that may not exist.
As an experiment, I also rm /design/my_design and reloaded - the clock groups were still not deleted !
Any ideas?
Thanks,
Steven