Hi
During comparison I get some non-equivalent points. Some non equivalencies are due to " DC due to clock/data interaction and DC due to asynchronous interaction". Due to this in Golden, the input to a select input of mux is 1 and that to the revised is X. What is the solution ?. Kindly reply.
assign #10 sig2=sig1;
I have not been able to find an attribute that shows whether a net in a scope is connected to a preset/clear of FF.
The only way I have found:
foreach FF in a scope {
foreach pin of this FF {
if { libpin of this pin is a {async_clear} } { set an async_clear net }
if { libpin of this pin is a {async_preset} } { set an async_preset net }
if { libpin of this pin is a {sync_clear} } { set a sync_clear net }
if { libpin of this pin is a {sync_preset} } { set a sync_preset net }
}
}
This is quite complicated, because in a certain block there can be several FFs each of which can be resetted in a different way, thus HW designer might need to create a TCL associative array to identify unique nets.
Is there an easier way to do this?
is externa dealy input is equel to settting setup time ?
external_delay –clock [find / -clock clock1] –input 200 -name in_con \
[find /des* -port ports_in/*]
externa dealy output is equel to settting hold time ?
external_delay -clock [find / -clock clock2] –output 400 -name out_con \
[find /des* -port ports_out/*]
Need a help on LEC: my LEC is clean between RTL vs. first compile netlsit from DC; however it failed on 30 points between RTL vs. compile_incr netlist.. I further did a gate-level LEC between compile netlist and compile_incr netlsit, but still same failing points as RTL vs. compile_incr. What could be the root cause of it and how to clear?
Appreciated any good advice/suggestions!
Bryan
Hi.
I'm having problems migrating from DC to RC in terms of reading HDL files.
1. I have a directory with subdirectories which include .v files - when I specify the main directory as the HDL search path, RC doesn't read the .v files under the subdirectories - any idea why?
The manual says it works like the search in unix therefore I don't understand why it doesn't try to read the subdirectories.
2. I have .v files which have commands like `include ../../ - when running RC, RC moves to a directory of its own with no regard to where the command was run from (unlike DC where if I run it from a certain directory, this directory is the reference for finding other files in case I use realtive statements such as ..) - therefore, those realtive `include commands doesn't work - any idea how to solve the problem?
Thank you in advance,
Adi.
Hi all,
One of the most common problems with LEC FEV is modules getting Blackboxed.
Can someone please add an exhaustive list or reasons that can cause it with a brief 2-3 lines description of each. - or a link to such a page.
Thanks
I am comparing pre-layout netlist and post-layout netlist in LEC.
Some of the blackbox pins are not connected in pre-layout netlist, which leads to non-equivalent points. I would like to ignore these.
Does anyone know how to set ignore pins for some blackbox pins in LEC? They are not primary input/output.
Thank you very much!
Hi, I have now seen this issue with two different designs and have not been able to figure out the root cause for this behaviour.
I have synthesized a design using RTL Compiler and have generated both mapped and an optimized netlist.
1. When I compare the RTL to mapped netlist (non-hierarchical comparison), I don't see any non-equivalent points.
2. When I compare the mapped netlist to the final optimized netlist, I don't see any non-equivalent points.
3. But when I compare RTL to final optimized netlist, I get non-equivalent points.
Looking into this matter in detail, I noticed that these non-equivalent points start showing up as soon as I run the first incremental synthesis on the mapped netlist.
Any ideas as to why the RTL to final netlist comparison are showing non-equivalencies?
I find difficulty doing equivalanece, after conformal ECO flow, due to unmapped points. Is there way, the Conformal ECO dumps svf file, which can be fed to equivalence check tool?
Hello.
What is the right way to insert clock gating in RC script?
How should i translate the following instructions form DC for RC ?
(DC) -->
set_clock_gating_style -sequential_cell latch \
-negative_edge_logic $CELL_NAME \
-positive_edge_logic $CELL_NAME \
-max_fanout 16 \
-minimum_bitwidth 4 \
-control_point before \
-control_signal scan_enable
---------------------------------------------------------------------------------------------------------
(RC) -->
define_dft shift_enable -name scan_enable -active high $CELL_NAME1
define_dft shift_enable -name scan_enable -active low $CELL_NAME2
set_attr lp_insert_clock_gating true
set_attr lp_clock_gating_min_flops 4 [find/design -design $DESIGN]
set_attr lp_clock_gating_style latch [find/design -design $DESIGN]
set_attr lp_clock_gating_control_point precontrol [find/designs -design $DESIGN]
set_attr lp_clock_gating_test_signal scan_enable $DESIGN
---------------------------------------------------------------------------------------------------------
Is it enough or there is something else needed?
Can anyone tell why this is happening
"Inserted DC(s) due to DFF clock/data interaction" and will it cause any false non -equivalency?
hi there,i am new to RTL compiler. I have delay element to synthesize in which the input is assigned to output after some delay .The state ment i used shown below.
assign #5 out=in;
But when i am synthesizing in RTL the delay is ignored. So are there any attributes i have to add to synthesis delays in RTL compiler? if not is there any other way to make delay elements? . I would be greatful to if you include sample code or snippet. Thanks in advance.
Hello.
What is the right way to insert 'remove_attribute' in RC script?
I know that this scirpt is one in one of the unsupported SDC commnads.
How should i translate this instruction form DC for RC ?
I guess...
get_attribute timing_case_disabled_arcs_by_mode instance_name or
get_attribute disabled_arcs_by_mode nand_inst {/design/top/~~~~}
Is it enough or there is something else needed?
Hello.
I'm trying to synthesis SPI core, but in the simulation occurs race conditions between signals SPI_CLK and system clock (clk) in "always" block:
always @(posedge clk)
spi_clk_r <= spi_clk;
How to avoid race condition in this case?
thanks
In my verilog code, I have XOR1 gate (in0, in1, out). Port "out" connects to the "D" input of a DFF. A code sample is below:
assign out = in0 ^ in1;
dff dff_0(.CLK(CLK), .in(out), .out(q));
..................
module dff(CLK, in, out);
input CLK;
input [127:0] in;
output reg [127:0] out;
always@(posedge CLK)
out <= in;
endmodule
However, after synthesis one additional XOR2 gate is inserted between XOR1 and DFF, i.e., "out" connects to one input of XOR2 and the output of XOR2 connects to "D" input of the DFF. I understand that the tool is doing some optimization related to my other logic. But how can I enforce the gate sequence in my verilog code in this specific case? (XOR1 connect to DFF directly) I am fine with restructuring the code.
BTW: I do not use any timing constraints.