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unmapped points with Conformal

April 24, 2014, 4:59 pm
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 I'm running LEC to verify that two RTLs are identical and getting a lot of unmapped points. I looked into a pair of key points, one from Golden and another from Revised,  which are supposedly corresponding each other and did a further investigation to find out why they weren't mapped.. Their outputs are not being used and the tool treats them as unreachable, hence unmapped, but I still need to map them to see whether RTLs are logically 100% identical.

I used -keep_unreach option, expecting the tool to compare the logic cone to the unmapped points, but they are still unmapped and the tool doesn't seem to compare them.

 How can I make the tool to compare the unmapped points due to unreachability ?

 

 Thanks

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LEC - Conformal RTL to netlist mismatch

July 11, 2012, 12:21 pm
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Hi, I have now seen this issue with two different designs and have not been able to figure out the root cause for this behaviour.

I have synthesized a design using RTL Compiler and have generated both mapped and an optimized netlist.

1. When I compare the RTL to mapped netlist (non-hierarchical comparison), I don't see any non-equivalent points.

2. When I compare the mapped netlist to the final optimized netlist, I don't see any non-equivalent points.

3. But when I compare RTL to final optimized netlist, I get non-equivalent points.

Looking into this matter in detail, I noticed that these non-equivalent points start showing up as soon as I run the first incremental synthesis on the mapped netlist.

Any ideas as to why the RTL to final netlist comparison are showing non-equivalencies?

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LEC mismatch b/w RTL and Lec-Friendly netlist

May 23, 2014, 11:36 am
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Hi,

     I am having the following issue and I am not been able to figure out the root cause for this issue.

     I am having a mixed design in which some portion of the design is RTL and some portion of the design is Netlist.

   I have done synthesis of this design and generated a lec friendly netlist(write_hdl -lec)

   I have done Lec b/w the lec-friendly netlist and the mixed design in both flat and hierarchical ways.

   The hierarchical comparision passed and the flat comparision is showing mismatches related to chipware components.

    Any idea on why this is happening?

    Is it required to do both flat and hierarchical comparision in this case?

   Awaiting for a sooner reply.

    Thank you all 

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what is the Purpose of initial_target attribute of a cost group?

May 23, 2014, 11:43 am
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Hi,

    I am having some timing violations in my design with a slack of around -2100ps. I have observed that all these violations belong to a same block. So,I have traced the clock(cost_group) of that block and I have used the following "set_attribute initial_target -100 [find / -cost_group cost_group_name]". Now the no of violations in my design decreased and the peak slack is only -1600ps. Can any one please tell me what is the reason for this and what is the use of the initial_target attribute of a cost_group? 

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LEC debug points report generation ???

May 29, 2014, 8:03 am
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LEC between rtl and netlist

i have black boxed all the logic blocks. 

assue there is no logic between inputs to till black boxes.

now i wanted to generate the report for each failed point with respect to inputs

please help

thanks

 

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How to force a small gate structure during RTL Compiler synthesis?

April 24, 2014, 11:09 am
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 In my verilog code, I have XOR1 gate (in0, in1, out). Port "out" connects to the "D" input of a DFF. A code sample is below:

assign out = in0 ^ in1;
dff dff_0(.CLK(CLK), .in(out), .out(q));
..................
module dff(CLK, in, out);
    input CLK;
    input [127:0] in;
    output reg [127:0] out;

    always@(posedge CLK)
        out <= in;

endmodule

However, after synthesis one additional XOR2 gate is inserted between XOR1 and DFF, i.e., "out" connects to one input of XOR2 and the output of XOR2 connects to "D" input of the DFF. I understand that the tool is doing some optimization related to my other logic. But how can I enforce the gate sequence in my verilog code in this specific case? (XOR1 connect to DFF directly) I am fine with restructuring the code.

BTW: I do not use any timing constraints.

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unmapped points with Conformal

April 24, 2014, 4:59 pm
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 I'm running LEC to verify that two RTLs are identical and getting a lot of unmapped points. I looked into a pair of key points, one from Golden and another from Revised,  which are supposedly corresponding each other and did a further investigation to find out why they weren't mapped.. Their outputs are not being used and the tool treats them as unreachable, hence unmapped, but I still need to map them to see whether RTLs are logically 100% identical.

I used -keep_unreach option, expecting the tool to compare the logic cone to the unmapped points, but they are still unmapped and the tool doesn't seem to compare them.

 How can I make the tool to compare the unmapped points due to unreachability ?

 

 Thanks

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LEC mismatch b/w RTL and Lec-Friendly netlist

May 23, 2014, 11:36 am
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Hi,

     I am having the following issue and I am not been able to figure out the root cause for this issue.

     I am having a mixed design in which some portion of the design is RTL and some portion of the design is Netlist.

   I have done synthesis of this design and generated a lec friendly netlist(write_hdl -lec)

   I have done Lec b/w the lec-friendly netlist and the mixed design in both flat and hierarchical ways.

   The hierarchical comparision passed and the flat comparision is showing mismatches related to chipware components.

    Any idea on why this is happening?

    Is it required to do both flat and hierarchical comparision in this case?

   Awaiting for a sooner reply.

    Thank you all 

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what is the Purpose of initial_target attribute of a cost group?

May 23, 2014, 11:43 am
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0
0

Hi,

    I am having some timing violations in my design with a slack of around -2100ps. I have observed that all these violations belong to a same block. So,I have traced the clock(cost_group) of that block and I have used the following "set_attribute initial_target -100 [find / -cost_group cost_group_name]". Now the no of violations in my design decreased and the peak slack is only -1600ps. Can any one please tell me what is the reason for this and what is the use of the initial_target attribute of a cost_group? 

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LEC debug points report generation ???

May 29, 2014, 8:03 am
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LEC between rtl and netlist

i have black boxed all the logic blocks. 

assue there is no logic between inputs to till black boxes.

now i wanted to generate the report for each failed point with respect to inputs

please help

thanks

 

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How to perform dynamic power analysis using RTL compiler

August 18, 2014, 8:19 am
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 Hi there,

 to approximate power consumption at an early design stage we want to generate the most accurate power reports one can get using a netlist from RTL compiler. Is EPS the right tool for this task ? We also want to annotate the switching activity using a vcd-File?

What is the best way getting accurate power approximations at this design stage?

 

Cheers,

Marten

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Using RC to estimate leakage & dynamic power from different synthesis runs

August 28, 2014, 11:00 am
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We are planning to using RC with a TCF (toggle) file to estimate leakage & dynamic power from different synthesis runs.

Yes, in a sense we are trying to get power estimates from many "what if scenarios". 

Has any one done this and care to comment on the steps and results on RC or other options?  Thanks. 

 

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Mining information from RTL Compiler log file.

September 22, 2014, 8:14 am
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Hi All !

My first time posting on this forum. :)

I have created a perl script that extracts the Path information that RC prints in the log file as it is working, and summarizes it. I have been finding this really useful to get a sense of which paths RC is spending the most effort on, and which would be most useful for me to improve in the RTL. I have found this report to give better guidance for RTL edits than the list of the paths in the RC generated report file, which while detailed and timing accurate, can include paths that just haven't been optimized much so far.

I wanted to get some feedback on this script from the experts here. Is what I am doing a good / robust idea ? Is there already some simpler way to get this information ? Any thing that could be done to make things better ?

Here's some sample output to explain what I mean

> syn_paths -min 40 rc.log

Number of times RC worked on a particular path (only paths with count >= 40) :
------------------------------------------------------------------------------
49      : cnfg_mode_fo2_reg_N__CK                 --> def_mem_A[N]                             
60      : abc_calc_grad_N_flop_q_reg_N__CK  --> abc_score_v_a_flop_q_reg_N__D
348     : xyz_fir2_mac_N_reg_N__CK               --> xyz_fir2_fir_out_reg_N__D             
--
960     : Total number of paths worked on by RC in full run.
--
-432.2  : Last WNS reported by RC.

From the output above, you could infer that the fir2 path is much more important to work on than the other paths, even if it is not first in the report.

Here's the full script source :  https://github.com/sgauria/scripts/blob/master/syn_paths

Thanks!

Sameer

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Using multiple libraries - mixed elaboration flow

September 23, 2014, 9:01 am
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I have a design in which I am testing multiple (similar) libraries. I have a top-level model in Verilog that references a subdesign twice. I would like to synthesize the subdesign with two different libraries to verify functionality under different test conditions post-fab. The subdesign itself references another design.

Right now, my RTL Compiler .tcl file looks something like this:

set_attribute lib_search_path {libpath1/ libpath2/}

set_attribute library {lib1.lib lib2.lib}

read_hdl -library lib1.lib mid_level_lib1.v bottom_level_lib1.v

read_hdl -library lib2.lib mid_level_lib2.v bottom_level_lib2.v

read_hdl top_level.v

elaborate top_level

synthesize -to_mapped -effort high

The mid and bottom level designs are identical except for the module names.

I assumed (perhaps incorrectly) that telling RC to read in my HDL using a specific library would synthesize it with that library.

I also tried a flow using multiple elaborations, and that really didn't work. It kept complaining of being unable to identify my top-level design. I tried another flow with synthesizing each mid/bottom level design in its respecitve libraries, saving the HDL, and synthesizing the top-level. Unfortunately, this complains of black boxes and "mixed elaboration flow [VLOGPT-652]."

Any help would be greatly appreciated.

P.S. What is the preferred way of including code on the forums? It looks like this forum does not support BBCode.
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RC response[TUI-39]after "report clock_gating"

October 2, 2014, 7:49 am
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Hi All,

     After "synthesis -to_mapped",when issuing "report clock_gating" command. The following error message appears:

====== 

Error   : Invalid or missing object for the attribute. [TUI-39] [get_attribute]

        : An object was not specified or the specified object was an invalid object type. There are 4 valid object types that can be specified as the final (third) argument when getting the 'lp_computed_toggle_rate' attribute. Valid objects are: pin, subport, port, and net.

1 

 ======

Although I can still write out the mapped netlist and sdc. But failed at the following command "write_et_atpg".In other words, no atpg database and I could not ignore this error. Someone tell me that RC may encounter some problem while trying to insert gated cell. But the log file did not show such a problem after "synthesis -to_mapped" command. I had checked the netlist and found that cells with RC_CGXX exists. I think that clock gated may works. Would you help me to solve this issue?Or tell me what else could I check.Thanks!

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How to compare 2 design entry HDL schematic?

December 22, 2014, 9:25 pm
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Hi,

How can I compare 2 design HDL schematic?  Any command or tool that can be used to compare 2 schematic?

thanks,

Maberu :)

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RTL compiler error

December 6, 2014, 2:11 am
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Sir, am getting this message when using RC.After showing this message tool is not responding.My other designs are working fine.But for this program sad1.vhd am getting correct output in NCSIM (also I was able to synthesize the design in xilinx ISE) so what may be the problem.

 Elaborating top-level block 'SAD' from file 'sad1.vhd'.
  Done elaborating 'SAD'.
        Trying carrysave optimization (configuration 1 of 1) on module 'SAD_csa_cluster_104'...
Info    : Done carrysave optimization. [RTLOPT-20]
        : There are 2 CSA groups in module 'SAD_csa_cluster_104'... Rejected.
        Trying carrysave optimization (configuration 1 of 2) on module 'SAD_csa_cluster'...
Info    : Done carrysave optimization. [RTLOPT-20]
        : There are 16 CSA groups in module 'SAD_csa_cluster'... Rejected.
        Trying carrysave optimization (configuration 2 of 2) on module 'SAD_csa_cluster'...
Info    : Done carrysave optimization. [RTLOPT-20]
        : There are 17 CSA groups in module 'SAD_csa_cluster'... Rejected.
        Trying carrysave optimization (configuration 1 of 2) on module 'SAD_csa_cluster'...
Info    : Done carrysave optimization. [RTLOPT-20]
        : There are 2 CSA groups in module 'SAD_csa_cluster'... Accepted.
        Trying carrysave optimization (configuration 2 of 2) on module 'SAD_csa_cluster'...
Info    : Done carrysave optimization. [RTLOPT-20]
        : There are 10 CSA groups in module 'SAD_csa_cluster'... Accepted.
Mapping SAD to gates.

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conformal lec : dump mapped points

December 19, 2014, 2:28 am
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Hi,

I would like to know how to dump the mapped points between RTL and netlist into a report file. Is there a command I can run or some option in the gui to make this happen?

I want to reuse this information else where in the flow. 

Thanks in advance.

Hari

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Digital library for RTL compiler

February 19, 2015, 3:09 pm
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I am trying to learn synthesis using RTL compiler.

Most of the tutorials I see online utilize PDKs which have to be licensed or digital libraries which have been modified by institutions. I was wondering if they are free digital libraries I can add to my Cadence Encounter suite so that I can synthesize circuits. I am not looking to fabricate anything but would like to learn how to use Encounter RTL compiler and P&R.

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Design entry hdl

March 7, 2015, 12:54 pm
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How can I add to the library a big number of companents of one famIly in a short period of time.

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