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RC

July 31, 2013, 7:52 am
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Hi Everyone,

When reading verilog (read_hdl -sv), first file is common variable definitions (like `define and localparam). There is no problem loading this file, however when loading the actual RTL design it cannot recognize the mentioned above variables (Error - undeclared).

If the same  variable definitions file added to RTL as `include it works, but there are too many RTL files and I have no permission to modify them.

Any idea what could the issue with loading it by (read_hdl -sv)?

Thanks a lot!

Boris



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Include a IP netlist during Synthesis of a complete design

August 14, 2013, 2:41 am
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I have an IP whose netlist is available. I want to include this netlist during Synthesis of my complete SoC. I do not want to modify anything inside this Netlist. 

 What are the steps to be followed during Synthesis? 

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how to define scan chains in RC

August 20, 2013, 3:32 am
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 Hi, 

 How to define the scan chains in RC and how to prevent the broken chains .

Tha basic question points to on how prevent the scan inputs of the scanable flops to get not tied up to 0.

 

Thanks 

Tanyacool

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Library requirements during elaboration stage

August 20, 2013, 2:52 am
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 Hi

I have a very basic question regarding the whole synthesis process. 

We say that before mapping the whole process goes technology independent (library), only during mapping it is technology dependent.

My question is then why do we have to source the libraries before the elaboration step which comes before the mapping stage. 

We can source it after the elaboration step also.

 

Thanks 

Tanvi 

 

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Force RTL compiler not to optimize certain part of the design

November 20, 2013, 1:55 pm
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Hi,

I have a verilog design which has an input A which is 128-bit. I would like to use assign statement to let A equals to a fix value.

But I don't want RTL compiler to optimize the logic associated with A, because I will give different values for A later in the spice level simulation. 

Is there any synthesis constraints that can achieve this purpose? 

 

Thank you very much! 

 

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re-target technology node

December 3, 2013, 6:55 pm
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Hi, I have a synthesize netlist with other process. Now, I wish to use other target other process without synthesize from RTL, can RC translate the netlist to other process? How?

 

Can someone help? I know the Sys* D* can do the tranlation, I am not really  sure how it did in RC. 

Thanks  

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How to set_current_module in RTL Compiler??

July 7, 2007, 1:00 pm
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Hi all,

I need to perform synthesis of a sub-block of the design. And then merge it with the top design.
I am using RTL Compiler.

In pks or build gates this was simple, we had the command set_current_module .. and one can then perform synthesis on a subdesign.

There seems to be no direct equivalent of set_current_module in RTL Compiler.

I found one command in RTL Comiler, derive_environment.
This promotes a subdesign to a topdesign.
So in design database we will now have
/designs/topdesign
/designs/subdesign_promoted_top

The synthesis which I perform on /designs/subdesign_promoted_top is now independent of actual topdesign.

This  works. But how can I later merge the
/designs/subdesign_promoted_top
into
/designs/topdesign ??

I see no way to do this in the userguide!

Can someone help me?

Thanks in advance,
Pradeep


Originally posted in cdnusers.org byspveer
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CIS Schematic Page numbering

December 20, 2013, 11:31 am
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Is there a way I can get the title block on my schematic sheets to automatically number themselves in CIS?  For example, let's say I have a 50 page schematic.  I would like to type in a total page count of 50 and have the "50" appear on every sheet  "SHEET X OF 50" and have the unique sheet number replace the "X".  Also, I would like to be able to only have to type in my schematic Dwg number one time and have it appear on all sheets in the title block  (DWG #:  ABC-123)  Any help would be appreciated. 
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Preserving structure in RTL Compiler

December 17, 2013, 6:46 am
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 Dear all,

I have a AND-OR structure written in RTL in a module. After the synthesis I see that the same logic is implemented using different logic elements in different modules. In one module I see AND-OR is formed with 4 instances, in other module with 5 instances.

Is there a way to tell RC to use exactly the same AND-OR structure in different modules, that are using same piece of RTL code?

Thanks,

Aram

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Instance name mismatch between .v and .sdf writen from RTL compiler

December 23, 2013, 7:32 am
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Hi,

I encountered a problem when I want to do simulation of the netlist after synthesis.  After I included $sdf_annotate in initial block and then elaborate.Many warning appears, like "W, SDFINF:instance w_ctr.wbin_reg\[2\2] not found at scope level <top-level. <./fifo.sdf, line12993>". It seems that the names of the instances are different in .v and .sdf. 

 in .v,  it is (INSTANCE w_ctr\.wbin_reg\[2\]),

but in .sdf, it defines as  df2sqpd \wbin_reg[2] (......);

I changed one of the name of instances to be the same, and then the warning of this instance disappers in elaborator. But I can't change all of them mannually, I don't want to do it by script neither, because I think there should be some configurations to fix this.

Could you help me with this??

 Any reply is appreciated. Thank you!

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how to identify unique nets connected to preset/clear pins of all FFs in a scope

January 7, 2014, 12:07 pm
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I have not been able to find an attribute that shows whether a net in a scope is connected to a preset/clear of FF. 

The only way I have found:

foreach FF in a scope {
 foreach pin of this FF {
  if { libpin of this pin is a {async_clear} } { set an async_clear net }
  if { libpin of this pin is a {async_preset} } { set an async_preset net }
  if { libpin of this pin is a {sync_clear} } { set a sync_clear net }
  if { libpin of this pin is a {sync_preset} } { set a sync_preset net }
}
}

This is quite complicated, because in a certain block there can be several FFs each of which can be resetted in a different way, thus HW designer might need to create a TCL associative array to identify unique nets.

Is there an easier way to do this?

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Algorithm used for implementation of Division

January 2, 2014, 11:00 pm
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Hi

What is the default algorithm used for hardware implementation of division operation when synthesised using RC Compiler. Like the code below  

begin

quot[n:0] = divd/dvsr;

remi = divd%dvsr;

end

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preserving a subdesign from optimization

December 30, 2013, 5:09 am
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I wont to generate a fixed delay, for which I have used multiple NOT gates and instantiated in the top design.  While synthesizing, RTL compiler optimizes the gates added and put a direct net without delay.  How to get such fixed delays synthesized??

 

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Conformal- LEC

January 16, 2014, 8:35 pm
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Hi When I run Hirarchial compare using conformal, write hier_compare dofile dofile.do is not created. It is throwing the error like "could not find the starting comment hierarchial do file generated by conformal when I run run hier_compare. When I setup the design I got the message like $ modules are output for Hierarchial do file yet the do file is not created. What may be the reason? I just used a simple verilog design. 
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conformal -Lec

January 28, 2014, 2:20 am
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I am verifying a RTL vs NEtlist created by synopsys DC compiler. Some modules are black boxes by the tool. I think they are some memory modules. What is the way to preserve the interface information of the black box ie only the boundary info. 
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conformal_lec 21.0

January 29, 2014, 2:33 am
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HI

I have an RTL and netlist from DC compiler. My library files are .lib files and I read them as liberty libary files. Do I have to designate the library both to RTL and Netlist. I f I do so I get some error like cant find a pin x. So I read the library only for the revised netlist. Also in non - equivalent points, the bbox is non equivalent since pin x in revised doesnt have matching pin in golden.   

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conformal

January 30, 2014, 2:20 am
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Does conformal lec support VSDC files which contain information about synthesis optimisations ?
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Design Entry HDL - Disabling Constraint Manager

February 5, 2014, 9:00 am
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 Is there a method to disable the Constrint Manager from Design Entry HDL?

 

I was able to make changes to an existign design and generate a netlist; however, the netlist appears to be missing 2 Constraint Manager files ( error message received when netlist was imported). I believe this may be related to opening the Constraint Manager prior to saving my file.

 

 

 

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Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist

March 6, 2013, 3:03 am
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I'm trying to setup flow for using CONFORMAL LEC with DC netlist, and facing few problems in mapping.

--> Conformal doesn't map the RTL(async neg reset) with its counterpart  in netlist(DC). 

---> Conformal Doesn't map the "SNPS_CLOCK_GATE_HIGH" latch 

 **************my dofile is as follows (till it goes into lec mode)

     reset

    set log file <  >

     "sourcing project specific variables"

    set undefined cell black_box

      add notranslate filepathnames <  >

      add search path

      read library -verilog2k  

       read design -noelaborate -verilog2k -nosensitive  -golden <>

         read design -noelab -systemverilog -nosensitive -golden <>

      elaborate design -golden <>

      read design  -verilog 2k -revised <>

        set flatten model -nomap -latch_transparent -latch_merge_port -seq_constant -gated_clock -seq_redundant -nodff_to_dlat_zero -verbose

 set system mode lec

 

*******************************************************************

 

please provide me the basic flow for CONFORMAL--DC netlist

 

regards,

rafeeq

 

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Logic Design Forum Posting Guidelines

February 6, 2014, 11:02 am
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Thanks for being part of the Cadence Community. Below are a few guidelines on using the forums.

  • Use descriptive subjects. "Problems with LEC mapping" is good. "Need help” isn’t.
  • Please start new threads for new topics. Don’t reply to existing threads with unrelated discussion. This helps users scan posted topics.
  • Helping other users is greatly appreciated by the community.
  • Searching http://support.cadence.com is good resource to get answers and file Support tickets.

Don’t forget to let others know about the Community Forums. http://www.cadence.com/community/forums/31.aspx

 

-ts

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