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Any comments on the RC Physical Timing co-relation with EDI?
Dear All, I have the database, which is physical optimized using the EDI flow & I want to further optimizations to reduce the slack, which i think is difficult in EDI,I thought of picking up RTL...
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Difference Between PLE, Spatial, Physical
Hi All, Can some one be able to explain, the fundamental differences between PLE,Spatial, & Physical of RC flows and the advantages over the other. In my View, PLE, Only requires Cap Table as an...
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VCD and irun
HiCan anybody tell me what switch I need to use to dump VCD file while using "irun" Thanks in advance
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How to see power trace
Hi,I have design using VAMS. I could generate VCD file from ncsim. And I want to see power trace while it is functional. (Dynamic power analysis). What tool will help me to do that? and what are the...
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clock tree design
Hi,We are designing a basic clock tree for a chain of flip-flops. The method that we are using is logic effort. Since the clock tree is just a bunch of inverters, G=1. So we only need to find out H...
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RTL Compiler: DFT Checks and non controllable/observable I/O
Hi,I am synthesizing a top level digital block that has interfaces to external pads and to a top level analog block.When I run DFT checks, it assumes that all ports are controllable, which is not the...
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CPF_Read Issue
Hello,I tried to read cpf file in RTL Compiler v8.0. the specification of isolation cells went fine however the cpf_read reports unsupported power_switch_cell. I used the following definifation for...
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CDC Functional Checks taking too much time.
Hi there,I am currently engaged in closure of CDC functional checks but to my frustration the run for CDC functional checks is taking a great deal of time and till now its just too slow to see it...
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RC-compiler Error create isolation rule and retention rule failed.....
Hello I am trying to synthesize my design in RTL Compiler v8.0 with CPF1.0 . i am using 45nm NanGateOpenCellLibrary. I am getting 2-Errors while synthesizing my design with CPF (PSO) method on RC...
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LEC - Conformal RTL to netlist mismatch
Hi, I have now seen this issue with two different designs and have not been able to figure out the root cause for this behaviour.I have synthesized a design using RTL Compiler and have generated both...
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.so cell import ?
Hello, I was given a component in a .so format (compiled verilogA would be my guess) and i would like to make it a cell in virtuoso to include it in a schematic and simulate it with spectre. Do you...
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dsn-files
Hello everyone,can someone me show the structure of dsn-files or a place I can find them? The background is the following: I' ve build a project in Capture and then created a netlist. But on this...
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Standard Cell Library Design
I am planning to design a standard cell library for 90nm process using Cadence 6.1.3 version. Can someone help me know how to use the parameterised-cell concept in designing the library. Any reference...
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RTL Compiler, Min Libraries and CPF
Hi,For synthesis (RTL compiler) I define a worst case libraries read_cpf -libraries, and in the CPF I usedefine_library_set -name my_lib_set _librares {libA_slow.lib libB_slow.lib libC_worst.lib} i.e....
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how to map a particular library cell to a component
In my design i have instantiated a structural mux. I want this mux to be mapped to one of the clock muxes in my design. But I want the tool to find out and use the clock mux of required strength. How...
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Should I bother about the PLL delay?
In my design I have 2 instances of PLL. The PLL A and PLL B are identical with two output pins (synchronous outputs). I have cascaded one of the output port of PLL A to PLL B. My module top/s_inst...
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how to add synthesizable delay in design
I am trying to add a delay of 3ns and 5 ns in my design but it not synthesizable in RC-compilor..anyone have idea how to add a synthesizable deslay in verilog........
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LEC report additional FF
We have a huge design with many redundant FFs. It's impossible to clean up the RTL as they are coming from many different IP vendors. Synopsys DC optimized out all those redundant FFs as their outputs...
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LEC and Designware components
Any method to resolve a blackboxed designware component on RTL netlist which does not match up to GATE level netlist? Due to scan insertion on the DW_ram* module in gate leve netlist, LEC will not...
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How to Simulate 64-bit VHDL Code in Cadence?
I am trying to simulate a VHDL code which have internally values exceeds the range of (-2**31 to 2**31). However, I can synthesize the code but I can't simulate it. I tried to change the attribute set...
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