Hello,
I was given a component in a .so format (compiled verilogA would be my guess)
and i would like to make it a cell in virtuoso to include it in a
schematic and simulate it with spectre.
Do you guys know how to do that ?
One told me to create a veriloga cellview then include this symbol in my
schematic and then to replace the .va of the netlist with the .so but i
get an error.
is this the idea to do it or something else ?
Thanks for helping, Let me know if you need more information.
Best
David
