Hello,
I want to know if there is a method in Cadence to calculate power for thousands set of input combinations separately for a logic circuit design.
Also, is there a way we can do the same by using Verilog?
PS: basically in my case, the total input combinations is approximately 60,000.
Thanks.
Dear all,
I'm currently trying to add scan-chain testability to a design that includes memories implemented with FIFOs. All FIFOs in the design are described at RTL-level using FlipFlops as basic storage elements, hence all these memories are fully-synthesized along with the remaining top-level logic. Since I'm not interested in replacing all FlipFlops of FIFOs with scannable FlipFlops part of the scan-chain, I'm trying to insert shadowlogic around them using the insert_dft shadow_logic command. Furthermore I'm only interested in by-passing all FIFOs inputs (my application doesn't require MBIST features for FIFO inputs). Nevertheless I want to make at least FIFOs outputs scannable. Hence my choice was to add scannable shadow-logic with register sharing as described in Design for Test in Encounter RTL Compiler documentation, pp. 220-224. Everything in the Cadence recommended flow works fine up to final scan-chain connection with a satisfactory percentage of ATPG coverage. At the end of the synthesis flow all FIFOs outputs are properly multiplexed with insertion of additional scannable-FlipFlops.
Due to a pad-count limited design the test clock adopted for the scan-chain and defined during the DFT setup is simply the main system clock. Indeed, with such a flow all extra-FlipFlops added by shadow-logic insertion introduce a lot of unwanted extra switching-power due to shadow FlipFlops always connected to the main clock. As a result, I would like to add clock gating to all extra FlipFlops inserted by RTL Compiler during shadow-logic insertion around FIFOs. I tried to perform this at RTL-level by hand, thus I've added an extra, unconnected input port clk_shadow in my design, which in turn is the main system/test clock with a test-mode controlled vetoing (clock gating is performed in the top-level wrapper with a dedicated latch/and block, I dont't care for the moment about this) . The clk_shadow signal is defined as an auxiliary test clock during the DFT setup, along with the main system/test clock clk :
define_dft \
test_clock \
-name scan_clk \
-period 25000.0 \
clk
define_dft \
test_clock \
-name shadow_clk \
-period 25000.0 \
-controllable \
clk_shadow
Since at the end of the flow I want to connect all scannable-FlipFlops into a unique scan-chain (including shadow-logic FlipFlops) both clocks are declared as part of the same test-clock domain
set_compatible_test_clocks -all
as suggested in
http://community.cadence.com/cadence_technology_forums/f/31/t/24651
After generic synthesis I run the insert_dft shadow_logic command and I specify as test clock the clk_shadow signal, as follows:
insert_dft \
shadow_logic \
-mode share \
-around [find / -instance Fifo*] \
-test_control scan_mode \
-test_clock_pin clk_shadow
After mapped synthesis I've two scan chains in my design, the first one directly driven by the system/test clock, the second one driven by the "clock-gated by hand at top-level" shadow-logic clock. Finally I run the connect_scan_chains command to merge scan-chains and thanks to the fact that the two clocks are into the same clock domain all extra shadow-logic scannable FlipFlops are connected into a unique scan-chain with others scannable FlipFlops driven by the system/test clock.
Actually, I'm not happy with such a solution that requires extra "tweaking" to RTL. I had a look to the insert_dft scan_power_gating command but its effective usage and application is not clear to me.
Can anyone suggest me the right way to add clock gating to all extra-FlipFlops part of a shadow logic structure?
Thanks in advance
Luca
When the tool is executing “synthesize -to_mapped -eff medium -no_incr”, the following messages start getting printed. There is no message code printed.
Removing external delay ‘clk_gating_check_15543’.
Removing external delay ‘clk_gating_check_15544’.
Removing external delay ‘clk_gating_check_15545’.
…
What do these lines mean? Can you suppress them?
Thanks,
Stephanie
While using IEEE1801 standard for power intent in synthesis with RTL compiler, how does one handle the RTL - instantiated low power cells? The tool is not honoring the hand instantiated cells and is inserting low power cells again.
Thanks in advance.
Hi,
Please help me with the problem below.
I am doing with RTL Compiler now and when I run the synthesis of my circuit, it really takes a lot of time.
Our server is separated into some virtual machines and I only use one of them. If anyone knows the way to improve the time of synthesis, could you please tell me?
I am sorry for my not-so-clear explanation.
Thank you in advance. Regards,
Minh
Hi,
I am new to synthesis and trying to learn.
I am reviewing Lint report from RTL compiler and it's telling that there are few clock pins in my design that are are either unconnected or driven by a logic constant.
These clocks have been defined in the constraints file properly and the also the clock report shows that these are the clocks with 50% duty cycle.
What can be the reason for that?
Regards,
Mickey
I am an innovus expert that has been pulled into the genus world out of necessity / similarity.
I am reading the same SOCV/POCV Liberty Variation Format dot.lib files into genus and innovus.
When I read the timing clean genus netlist into innovus and report timing on the initial preplace Zero Wire Load,
I am seeing large slack TNS/WNS violations when innovus SOCV is enabled.
+--------------------+---------+---------+---------+---------+
| Setup mode | all | reg2reg |reg2cgate| default |
+--------------------+---------+---------+---------+---------+
| WNS (ns):| -0.469 | -0.469 | 0.154 | -0.443 |
| TNS (ns):|-12153.9 |-11186.7 | 0.000 |-967.159 |
| Violating Paths:| 58393 | 55795 | 0 | 2598 |
| All Paths:|1.64e+05 |1.55e+05 | 22 | 11065 |
+--------------------+---------+---------+---------+---------+
OUCH !!
Is SOCV supported in genus?
Shawn
Hi,
While referring to 1801 UPF standard, I came across the below statements in "create_supply_port" command section:
a) The LowConn of an input port is a source.
b) The HighConn of an input port is a sink.
I am confused over these statements. For instance regarding point-(a), from my understanding, the LowConn side (i.e in the child instance) of a input port should be a sink (i.e load). Because input supply port is the one that provides power to the internal circuit/logic of the instance. Hence this circuit/logic should act as a sink (i.e load) to the input port. But why is the standard specifying it a source? Am I missing something here?
Will really appreciate, your help in understanding this better.
Regards
Kishore.
Hi,
I want to look at the net arc delay for a given from_pin and to_pin on a net. Is there a command that can get me that? I tried "report net_delay_calculation" but it says that this command is not supported on physical nets.
Ankur
Hi all,
I getting an error " <TA_1014> Detected a missing clock arrival for one transition because a timing arc of this pin". As from I searched on Cadence Support, maybe the lib has only the rise_transition or fall_transition information for an arc... but I checked the lib of the cell and there are both rise_transition and fall_transition information in the lib ...
Could you please give me some hints for this issue.
Best & Regards,
TungVo
Hi,
I am trying to compile a design with Incisive, using "irun" commands.
The design was previously compiled and tested with VCS.
When compiling some VIPs, I encountered multiple times the following error:
In particular it seems related to the declaration of "interface class name" inside the code.
I could not find anything related to this problem and it prevents the compilation to succeed.
The swithces I am currently using are " -elaborate -sv -64bit -uvmhome CDNS-1.2"
Thanks in advance for any help.
Luca
Hi,
I'm a TA for a digital design course. While doing synthesis, some students are getting following warnings.
Warning : A connection to a super-threading server has been lost unexpectedly. [ST-113]
: The server was process 'xxxx' in this host.
: RC will attempt to continue without that server.
RTL Compiler remains stuck there even if left for overnight. Any idea what could be causing that?
Hi,
i have designed half adder circuit in transistor level using or cad pspice simulation tool,
how to calculate the delay in orcad pspice for the schematic which i have designed in pspice.
Thanks in advance.
Using Concept, on a hierarchical design is it possible to generate a report that details components used per page within a block?
I know PHY_PAGE will list the page number within a block but not actually give the block detail i.e. CORE, FPGA, POWER etc.
The report I am looking to generate would look like the following:
REF DES HIERARCHICAL BLOCK PHY_PAGE PART_NAME DEVICE_TYPE
Thank you in advance for any help.
I came across a statement in some training videos that understanding how to effectively create cost groups in a design will aid in achieving the best results. The default for Genus is to create separate cost groups for each clock in a design, but I am going to have to do some weird things earlier and need to know how to create my own cost groups in a manner that Genus still is okay with. Therefore, my question is the following: where can I find documentation that explains how to properly configure cost groups, as well as explanations of what the cost grouping/path grouping tool is used for. I cannot find anything on the website or on the internet about this even though Cadence emphasizes it as important.
For instance, something like:
irun top.v -f manifest.f +define+FPGA=1 +default_nettype=none
As opposed to putting:
`default_nettype none
Within the files themselves.
Either a direct way or a workaround to implement this would be extremely helpful for me. Thank you very much.
hi there
i'm having trouble on counter simulation. where can i find a counter library with psipce model to run?
for example i want to simulate cd4060 or 74867, what should i do?
many thanks
Hi,
I've been using the 'auto_ungroup = false' attribute on the root design in Genus to keep a clear hierarchy in my design, as it is easier to partition later on.
Weirdly enough, a post-synthesis simulation with auto_ungroup enabled works fine, while disabling the property causes the simulation to fail (function wise).
First, is this a bug or a hidden feature? Secondly, as I want to keep my hierachy, are there other solutions available?
(The design is a simple SoC with RISC-V cpu, I rather not spend time on debugging if I can change just one synthesis attribute)
Thanks.
Hi all,
I know this will sound like a silly question, but I have only limited access to the tool documentation (I have access to Cadence Tools via University Program, but that's managed by a third party and they didn't yet provide access to the documentation...)
Question is: how can I change the value of a root attribute via command line?
In the old RTL Compiler I would change synthesis effort through synthesize -effort {low|medium|high}, now in the new Genus UI I see there're root attributes syn_generic_effort and syn_map_effort that control the effort, but I didn't find anywhere how I can change the value of these attributes...
Any help would be appreciated (also in the form of references to other documentation)! Thanks in advance
Dear all,
in my design I use as an input port the following statement logic [15:0] d [15:0]. This statement is supposed to be the input of a 16 to 1 / 16 bits wide inputs multiplexer.
Obviously synthesis is going pretty well since I get an output netlist. Though when I try to simulate using the same testbench I used for pre-synthesis simulation, using the following statement for connectio, xcelium throw an error
// internal testbench code
logic [n-1:0] data_write [n-1:0];
reg_shift_milpisso rs0 (.d(data_write),.*);
// xcelium error
xrun(64): 17.10-s010: (c) Copyright 1995-2018 Cadence Design Systems, Inc.
xrun: *N,CLEAN: Removing existing directory ./xcelium.d.
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
reg_shift_milpisso rs0 (.d(data_write),.*);
|
xmelab: *E,CUVPOM (./reg_shift_milpisso_tb.sv,28|28): Port name 'd' is invalid or has multiple connections.
xrun: *E,ELBERR: Error during elaboration (status 1), exiting.
the synthesis resulting netlist is the following
// Generated by Cadence Genus(TM) Synthesis Solution 16.23-s049_1
// Generated on: Jul 16 2018 14:49:52 CEST (Jul 16 2018 12:49:52 UTC)
// Verification Directory fv/reg_shift_milpisso
module reg_shift_milpisso(clock, reset, op, sel, \d[0] , \d[1] , \d[2]
, \d[3] , \d[4] , \d[5] , \d[6] , \d[7] , \d[8] , \d[9] , \d[10] ,
\d[11] , \d[12] , \d[13] , \d[14] , \d[15] , q);
input clock, reset;
input [1:0] op;
input [3:0] sel;
input [15:0] \d[0] , \d[1] , \d[2] , \d[3] , \d[4] , \d[5] , \d[6] ,
\d[7] , \d[8] , \d[9] , \d[10] , \d[11] , \d[12] , \d[13] ,
\d[14] , \d[15] ;