Hi,
I am new to synthesis and trying to learn.
I am reviewing Lint report from RTL compiler and it's telling that there are few clock pins in my design that are are either unconnected or driven by a logic constant.
These clocks have been defined in the constraints file properly and the also the clock report shows that these are the clocks with 50% duty cycle.
What can be the reason for that?
Regards,
Mickey
I am an innovus expert that has been pulled into the genus world out of necessity / similarity.
I am reading the same SOCV/POCV Liberty Variation Format dot.lib files into genus and innovus.
When I read the timing clean genus netlist into innovus and report timing on the initial preplace Zero Wire Load,
I am seeing large slack TNS/WNS violations when innovus SOCV is enabled.
+--------------------+---------+---------+---------+---------+
| Setup mode | all | reg2reg |reg2cgate| default |
+--------------------+---------+---------+---------+---------+
| WNS (ns):| -0.469 | -0.469 | 0.154 | -0.443 |
| TNS (ns):|-12153.9 |-11186.7 | 0.000 |-967.159 |
| Violating Paths:| 58393 | 55795 | 0 | 2598 |
| All Paths:|1.64e+05 |1.55e+05 | 22 | 11065 |
+--------------------+---------+---------+---------+---------+
OUCH !!
Is SOCV supported in genus?
Shawn
Hi,
While referring to 1801 UPF standard, I came across the below statements in "create_supply_port" command section:
a) The LowConn of an input port is a source.
b) The HighConn of an input port is a sink.
I am confused over these statements. For instance regarding point-(a), from my understanding, the LowConn side (i.e in the child instance) of a input port should be a sink (i.e load). Because input supply port is the one that provides power to the internal circuit/logic of the instance. Hence this circuit/logic should act as a sink (i.e load) to the input port. But why is the standard specifying it a source? Am I missing something here?
Will really appreciate, your help in understanding this better.
Regards
Kishore.
Hi,
I am referring to IEEE 1801-2015 standard's "4.5.5 Supply Equivalence" section. I do not see the standard defining how 2 resolved nets can be called electrically equivalent. Can someone help me out on this?
Thanks,
-Kishore
Hi,
Is there a techincal user forum, in Cadence or Accellera, that shows / discuss topics on UPF low power standard?
Regards
Kishore
I want to implement 6 buffer delay in my design and I am writing set_dont_touch i _delay_1 true command where i_delay_1 is instance name but it gives an error like cannot preserve unmapped or partially mapped design, first synthesize with mapping
Hello,
I am synthesizing a 32-bit multi bit multiplexer (with cell instance of 100)and generating power reports by using .SAIF file that comes from simulation tool.
Initially I generating various .saif files by making various changes (no .of stimuls patterns) in the testbecnch file , But keeping the simulation time constant in all cases.
my question is, In various runs for various .saif files, my synthesis tool shows different dynamic power which is acceptable but why the leakage power is also changing ???
Regards,
Anil kumar k
Hi everyone,
I was wondering whether it is possible to set a maximum value for fan-out (or the slew rate) at the output of each cells during synthesis, I've seen some commands however they mostly are for the output pins and not applicable for the output of each cell. Is there any command in RC that can do it?
Regards,
Medya
Hi,
What is the industry SOC DFT methodology to cover multiple physical blocks each one containing multiple IPs and using standard bus protocols like AXI, APB, AHB
and each physical block needing to communicate to other ones using AXI protocols ?
Develop DFT controller and scan chains for each big physical block (with many IPs)
and then use a master DFT controller to control each of the physical blocks and possibly control multiple DFT controllers together ?
How to ensure DFT works with busses like AXI which use point to point protocols and register slices might be inserted in the physical layout ?
Seems like multiple DFT controllers would need to coordinate working together in order to make this happen.
Any tips and recommendations are appreciated.
Thanks,
David
when I finished sythesis by RC, I got the area report like below:
************* Area *************
Instance Cells Cell Area Net Area Total Area
-----------------------------------------------------------------------------------
alu 22395 41896 53817 95714
ops1_add_25 15332 26677 36311 62988
......
could anyone tell me how get the memory area information ?
I have checked the command "report area" and don't find useful option for this.
thanks in advance
Hi,
I am trying to synthesize VHDL files using RTL compiler and created the netlist file. My design is hierarchical with submodules. However, the netlist created with a submodule name. Is it due to some optimization? How can I change this? My script is as below
set_attr lib_search_path /cad/FOUNDRY/digital/90nm/dig/lib
#set_attr hdl_search_path ../rtl/
set_attr library /cad/FOUNDRY/digital/90nm/dig/lib/slow.lib
read_hdl -vhdl {/home/manideepam/NOC/my_package.vhd /home/manideepam/NOC/my_switchcontrol.vhd /home/manideepam/NOC/my_buffer.vhd /home/manideepam/NOC/my_crossbar.vhd /home/manideepam/NOC/RouterBL.vhd /home/manideepam/NOC/RouterBC.vhd /home/manideepam/NOC/RouterBR.vhd /home/manideepam/NOC/RouterCC.vhd /home/manideepam/NOC/RouterCL.vhd /home/manideepam/NOC/RouterCR.vhd /home/manideepam/NOC/RouterTL.vhd /home/manideepam/NOC/RouterTR.vhd /home/manideepam/NOC/RouterTC.vhd /home/manideepam/NOC/NOC.vhd}
elaborate NOC
read_sdc NOC_constraints.sdc
#read_sdc constraints_top.sdc
check_design NOC -unresolved
synthesize -to_mapped -effort medium
#write_sdf -timescale ns -nonegchecks -recrem split -edges check_edge > delays.sdf
write_hdl NOC > NOC_netlist.v
write_sdc NOC > NOC_rc_sdc.sdc
write_script NOC > NOC_rc_sdc.g
report power > NOC_power.rep
report timing -lint > NOC_timing.rep
report gates > NOC_cell.rep
report area > NOC_area.rep
gui_show
Hello,
I've got strange messages when passing elaborate tcl command:
Info : Found unusable library cells. [LBR-415]
: Library: 'CORE65GPSVT_nom_1.00V_25C.lib', Total cells: 866, Unusable cells: 81
Info : Found unusable library cells. [LBR-415]
: Library: 'IO65LPHVT_SF_2V5_50A_7M4X0Y2Z_nom_1.00V_2.50V_25C.lib', Total cells: 8, Unusable cells: 8
I'm using genus 16.2 and STMicroelectronics 65nm design kit.
Does anyone know that kind of problem?
Regards,
Rémi Pallas
Hello,
I've got strange messages when passing elaborate tcl command:
Info : Found unusable library cells. [LBR-415]
: Library: 'CORE65GPSVT_nom_1.00V_25C.lib', Total cells: 866, Unusable cells: 81
Info : Found unusable library cells. [LBR-415]
: Library: 'IO65LPHVT_SF_2V5_50A_7M4X0Y2Z_nom_1.00V_2.50V_25C.lib', Total cells: 8, Unusable cells: 8
I'm using genus 16.2 and STMicroelectronics 65nm design kit.
Does anyone know that kind of problem?
Regards,
Rémi Pallas
Hi,
I have noticed that there are always memory libraries for the foundry provided PDKs.
I suppose that these memory library are for digital implementations. That is, using synthesis tools, the memory could be utilized.
But I am wondering whether the memory libraries are a must?
I mean, if I have a small design, such as encryption or decryption core.
I have tried that such a small core could be synthesized by using synthesis tools without the memory libraries.
I am wondering how the synthesized circuits realize the memory functional cells without the memory libraries?
And, what is the difference between the synthesized design with and without the memory libraries?
Thanks.
Jerry
Hi,
We are switching over to RTL Compiler. I am moving our scripts over to the RTL Compiler flow.
1) When I type pwd into RTL Compiler I get back / . I need the path where I started RTL Compiler, similar to doing a pwd in linux. Is there a command to get the full path and not just the path from where you started RTL Compiler?
2) The following option is not available in RTL Compiler. How do I set the multicore CPU option in RTL Compiler?
set_host_options -max_cores 2
3) Is there an RTL Compiler command that is similar to the synopsys command: synopsys_program_name
Thanks,
Stephanie
Hello,
I am trying to run LEC on a netlist from DC (This netlist has already passed Formality successfully).
When running in LEC, I have about 30 DFFs that are not mapped in the golden, since DC removed them. My suspect is that DC removed them due to optimization of feedbacks (means, each of those DFFs have its output connected back to its own input rather than other inputs, so DC optimizes these cases as a special case of floating output).
I've tried to use the commands: 'set_flatten_model -seq_constant -seq_constant_feedback'
and: 'eval read_setup_info $DC_LOG -type DCLOG'
None of these helped.
How can I help LEC deal with this case?
Thanks!
Adi
I am trying to use the get_libs command with a regular expression. The following is returning an error for me as the regular expression is not working. It is trying to evaluate [sft] instead of using it in the regular expression. How do I write this line of code to work properly?
[get_libs -regexp "scs8ls_[sft][sft]_.*"]
rc:/> [get_libs -regexp "scs8ls_[sft][sft]_.*"]
invalid command name "sft"
Thanks,
Stephanie
Hi,
Is there a command or switch in RTL compiler that will add pg pins also in the synthesized netlist. This can be done at encounter but wanted to know if same result can be achieved in RTL compiler.
Thanks,
Regards,
-DN
Hello everybody
I'm designing a fully synchronous digital block for a biomedical application. Since I have a very slow dynamics in my design, I need a slow clock. So I expect to obtain a small power in the synthesis report (I assume if I decrease the speed of the clock the total power should be decreased). However, when I decrease the input clock (by assigning a large number for -period of my external clock) this error appears on screen:
Unsupported SDC command option. [SDC-201] [create_clock]
The 'create_clock' command on line '7' in the SDC file 'calcium.sdc' only accepts values less than 214748.364 for the '-period' option.
Could not interpret SDC command. [SDC-202] [read_sdc]
: The 'read_sdc' command encountered an error while processing this command on line '7' of the SDC file 'calcium.sdc': create_clock -name clk -period 125000000 [get_ports 'clk'].
The error stems from the large number that I have dedicated to -period in SDC file. I dont know how to define a slow clock for my design and check the coressponding power and area!
Kind regards,
HS88.
Could not interpret SDC command. [SDC-202] [read_sdc] : The 'read_sdc' command encountered an error while processing this command on line '7' of the SDC file 'calcium.sdc': create_clock -name clk -period 125000000 [get_ports '
Hi,
I am using the following command to elaborate my design. The design name is updated with the parameter names and values. I do not want the design name to change.
elaborate $DESIGN_NAME -parameters $cyDesign(ELAB_PARAMS)
I have tried to use the change_names command to fix this. I have come up with a hack, but I need a more generic solution.
I have tried using the following change_name options with no luck:
-replace_str : This needs other options and I couldn't get it to work. I just want to put the original name with this command. How do I use this option properly? Can you post the code for using this option to change the design name.
-map {{"from" "to"}} : I tried putting the whole from and to names in here, but that doesn't work to fix the problem
My hack is below, but I just simply want to replace the design name and not do this weird hack.
change_names -design -max_length [expr [string length $DESIGN_NAME] + 2]
Please help!
Thanks,
Stephanie