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What kind of flops does state retention synthesis take?
I have designed my own standard cell library using some commercial process technology. I am trying to synthesize a large design that is implemented as a retimed module whose latency is controlled by...
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How to interpret area reported by Genus in mm2
I'm a student and new to ASIC design. Kindly let me know the steps I need to follow to interpret Total Area: 554138.039 as reported by Genus, in mm2. I don't see any units in lib files, although gate...
View ArticleGenus: Problem with long module name due to parameter types
Hello,I'm currently synthesizing a SytemVerilog design using Genus 19.11. In the report, I'm getting the information, that there is one subdesign with a long module name. It turned out that this long...
View ArticleGenus synthesis report
In the synthesis report, I see "No Paths" under "Critical Path Slack" associated with certain clocks. What does this mean? There is no critical paths associated with this clock at all?
View ArticleCan Joules Report on wasted power on the inputs of a gated flop?
The scenario is where the inputs of a flop are toggling, due to upstream logic/flops being on.But that upstream logic should've been gated off and wasn't. Yet the downstream flop is properly gated.Can...
View Articlexmvlog: *E,MULPAK
I am trying to simulate a design with multiple packages . I use the "-makelib/-endlib" options in xrun to specify all of the files . However, I have run into a problem with packages. In this case, I...
View ArticleBest library structure (worklibs)
Hello, I would like to ask for your expertise about setting for best library structure (worklib). Will it be better to have multiple libraries ( library per part classification : resistor, capacitor...
View ArticleGenus : Tool coming out with "Killed"
Hi , I am a newbie running genus tool. I have a parameterized design that i am trying to elaborate and synthesize using genus. When i source the tcl script, it runs for a long time and then the tool...
View ArticleRTL Design of SPI
Hello Everyone,I am new to this forum, so, please advise in case of any mistakes.I am trying to work on a self-project wherein I intend to develop an RTL Design of SPI using SystemVerilog. I have read...
View ArticleReading data from a file and assign those into a parametric array in verilogAMS
Dear All,I want to read data from a file and assign those into a parametric array in verilogAMS.How can it be done ?Kind Regards
View ArticleCan we do synthesis by using variables in generate block
Dear All,I want to synthesize a logic iteratively based on the values of the some variables by using generate construct.The portion of the generate block is shown below.Could any body please tell...
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Genus Synthesis not preserving register for sequential logic with pragma.
Hi All,I am using /*cadence preserve_sequential */ pragma to preserve reg type in sequential logic and using "// cadence keep_signal_name clkdiv13 syn_keep=1" to preserve a wire named clkdiv13 in the...
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when i use the elc, i found these problems, please help me!
When I was using ELC simulation, the following error occurred. Only one vector failed.When I checked the log file, the following error occurred. Who can help me？
View Articlecadence Digital design
Hello everyone,Good morning all, while I was pasting the command in scriipt file, i have the following error.cadence@cad07 xorgate]$ genus _f script.tclbash: genus: command not found...code:module...
View ArticleCadence Encounter and Innovus Library Compatibility.
Hello Everybody:I am new to using Cadence Logic Synthesis and Physical Design tools (Genus, Innovus, Encounter). I wish to perform these, however, I wished to know if the Nangate 45nm Open Cell Library...
View ArticleEnd cap/boundary cell in my pdk from LFoundary
Hello everyone,I am designing a decoder using custom digital compiler. I could not find End cap cell and boundary cells in my pdk. There are few cells which I don't understand but I am not sure what...
View ArticleDecoder standalone synthesis in Genus
Hello everyone,I am designing a mixed signal vision sensor where a decoder is required to select the rows of image sensor sequentially. So, my target is to synthesize the decoder separately in the...
View ArticleHELP WITH Integral nonlinearity (INL) and differential nonlinearity (DNL) of...
Hi, I'm developing an A/D converter in the LTspice program. However, the circuit presented problems and I only have the transfer curve.I need to do a performance tests, find the INL and DNL error, how...
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Digital Custom Placer Via not placing
Hello everyone,I am designing a decoder using custom digital placer. I did power ring and was in process to place vias. But it is not placing Vias but showing the attached lines in the CIW window. I...
View ArticleConstraining some nets to route through a specific metal layer, and changing...
Hello All:I am looking for help on the following, as I am new to Cadence tools [I have to use Cadence Innovus for Physical Design after Logic Synthesis using Synopsys Design Compiler, using Nangate 45...
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