Hello everyone,
I am designing a mixed signal vision sensor where a decoder is required to select the rows of image sensor sequentially. So, my target is to synthesize the decoder separately in the genus. Since the decoder is a combinational block, I am using a virtual to time the different constraints. I am using the attached verilog code for decoder synthesis. I am also attaching the constraint file. What I am getting at the output is a glitchy output when I am testing it (virtuoso environment)?Please let me know if any other information is needed.community.cadence.com/.../decoder.txtcommunity.cadence.com/.../decoder_5F00_constraint.txt