Problem occurs when reading vcd in RTL Compiler

Dear all,

I need to analyze the power consumption using RTL Compiler based on the VCD file generated by ModelSim. I have two files:

gcm.v (This is the main circuit. Module name is "gcm")

tb.v (This is the testbench. Module name is "tb", and "gcm" is instantiated as "gcm_tb")

The command to generate vcd file is in tb.v as below:

  $dumpfile ("testb. vcd");

  $dumpvars (1, testbench.gcm_tb);

Here is my script for RTL compiler:

set_attribute lib_search_path /opt/cadence/local/FreePDK45/osu_soc/lib/files

set_attribute library {gscl45nm.lib}

read_hdl -v2001 tb.v

elaborate

synthesize -to_mapped 

read_vcd -vcd_module gcm_tb -module gcm -static testb.\ vcd

write -mapped > gcm_synth.v

report power > power.txt

exit

 RTL compiler gives me the same power numbers with and without the VCD file. What is the reason for this? 

 Thank you!