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unmapped points with Conformal
I'm running LEC to verify that two RTLs are identical and getting a lot of unmapped points. I looked into a pair of key points, one from Golden and another from Revised, which are supposedly...
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LEC - Conformal RTL to netlist mismatch
Hi, I have now seen this issue with two different designs and have not been able to figure out the root cause for this behaviour.I have synthesized a design using RTL Compiler and have generated both...
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LEC mismatch b/w RTL and Lec-Friendly netlist
Hi, I am having the following issue and I am not been able to figure out the root cause for this issue. I am having a mixed design in which some portion of the design is RTL and some portion of...
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what is the Purpose of initial_target attribute of a cost group?
Hi, I am having some timing violations in my design with a slack of around -2100ps. I have observed that all these violations belong to a same block. So,I have traced the clock(cost_group) of that...
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LEC debug points report generation ???
LEC between rtl and netlisti have black boxed all the logic blocks. assue there is no logic between inputs to till black boxes. now i wanted to generate the report for each failed point with respect...
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How to force a small gate structure during RTL Compiler synthesis?
In my verilog code, I have XOR1 gate (in0, in1, out). Port "out" connects to the "D" input of a DFF. A code sample is below:assign out = in0 ^ in1; dff dff_0(.CLK(CLK), .in(out), .out(q));...
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unmapped points with Conformal
I'm running LEC to verify that two RTLs are identical and getting a lot of unmapped points. I looked into a pair of key points, one from Golden and another from Revised, which are supposedly...
View ArticleClik here to view.
LEC mismatch b/w RTL and Lec-Friendly netlist
Hi, I am having the following issue and I am not been able to figure out the root cause for this issue. I am having a mixed design in which some portion of the design is RTL and some portion of...
View ArticleClik here to view.
what is the Purpose of initial_target attribute of a cost group?
Hi, I am having some timing violations in my design with a slack of around -2100ps. I have observed that all these violations belong to a same block. So,I have traced the clock(cost_group) of that...
View ArticleClik here to view.
LEC debug points report generation ???
LEC between rtl and netlisti have black boxed all the logic blocks. assue there is no logic between inputs to till black boxes. now i wanted to generate the report for each failed point with respect...
View ArticleClik here to view.
How to perform dynamic power analysis using RTL compiler
Hi there, to approximate power consumption at an early design stage we want to generate the most accurate power reports one can get using a netlist from RTL compiler. Is EPS the right tool for this...
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Using RC to estimate leakage & dynamic power from different synthesis runs
We are planning to using RC with a TCF (toggle) file to estimate leakage & dynamic power from different synthesis runs.Yes, in a sense we are trying to get power estimates from many "what if...
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Mining information from RTL Compiler log file.
Hi All ! My first time posting on this forum. :)I have created a perl script that extracts the Path information that RC prints in the log file as it is working, and summarizes it. I have been finding...
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Using multiple libraries - mixed elaboration flow
I have a design in which I am testing multiple (similar) libraries. I have a top-level model in Verilog that references a subdesign twice. I would like to synthesize the subdesign with two different...
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RC response[TUI-39]after "report clock_gating"
Hi All, After "synthesis -to_mapped",when issuing "report clock_gating" command. The following error message appears:====== Error : Invalid or missing object for the attribute. [TUI-39]...
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How to compare 2 design entry HDL schematic?
Hi,How can I compare 2 design HDL schematic? Any command or tool that can be used to compare 2 schematic?thanks,Maberu :)
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RTL compiler error
Sir, am getting this message when using RC.After showing this message tool is not responding.My other designs are working fine.But for this program sad1.vhd am getting correct output in NCSIM (also I...
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conformal lec : dump mapped points
Hi,I would like to know how to dump the mapped points between RTL and netlist into a report file. Is there a command I can run or some option in the gui to make this happen?I want to reuse this...
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Digital library for RTL compiler
I am trying to learn synthesis using RTL compiler.Most of the tutorials I see online utilize PDKs which have to be licensed or digital libraries which have been modified by institutions. I was...
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Design entry hdl
How can I add to the library a big number of companents of one famIly in a short period of time.
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