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Irun driver contention with SystemVerilog port defaults (15.20.001)
Hi folks,I am simulating a mixed language design with Irun 15.20.001 with DUT toplevel being Verilog and lower level files being SystemVerilog and VHDL. Irun is seeing driver contention on...
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Differences between "report power" and "report scan_power"
Hello,I make a rtl synthesize in genus. I use both "report power" and "report scan_power" commands like below.report power -hier > power.repreport scan_power -clock 100 > scan_power.repAlso, I...
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Inverter Chain Synthesis
Hello!I'm trying to synthesize a chain made up of 8 inverters, but the synthesis tool optimizes it and generates a design which is composed of just 1 single inverter.How do I tell it not to...
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Re-characterizing a tap-less cell library (Cadence Liberate)
Hi All,I want to re-characterize the existing library to a lower supply voltage. I have been provided the extracted (with parasitics) netlist (.cir) of this tap-less cell library by the vendor. > So...
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How to determine electrical equivalence of resolved nets, with UPF 1801...
Hi,I am referring to IEEE 1801-2015 standard's "4.5.5 Supply Equivalence" section. I do not see the standard defining how 2 resolved nets can be called electrically equivalent. Can someone help me out...
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problem with "REPORT RULE CHECK" command using conformal
Hi,I am using Conformal version 16.1 to run rule checks and fix the issues. I am able to successfully read the design, and see the issues using "report rule check" command. I am also able to waive the...
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RTL compiler crash
Hello,I am trying to synthesize my design using Cadence RTL compiler Ultra. However, it invariably crashes after synthesizing to generic gates in the "Multi-threaded Virtual Mapping" Phase. I am using...
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for choosing the frequency range of any digital circuit
hello,can any when suggesting how we can decide any digital circuit work up to which frequency range ??how we take the range of frequency for plotting the graph between power, delay, and PDP??
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Error in Cadence RTL Compiler when estimating Power using VCD
Hi, I want to estimate the power using a VCD I dump directly from my testbench. The commands I use for dumping the VCD are:$dumpfile("OneExample.vcd");$dumpvars(0, Top_tb.CyNAPSE);(testbench file is...
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Genus synthesis syntax Foreach
Hi allCan we use such syntax in genus synthesisBecause I ve seen such syntax is not supported with latest version The data_reg is a packed array of data_bitforeach (data_reg.data_bit [idx])..The RTL...
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Formatting of concept HDL schematic pages
I am working with Concept Entry HDL and with a project that has about 100 pages of different schematics.I am make it easier to understand the use of each schematic and want to create small sub-groups...
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functional equivalence check between system verilog and schematic
Hi,I am wondering if lec -gxl can handle system verilog RTL behavioral code against schematic.Satendra
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CONFORMAL ECO : SPARE CELLS NOT MAPPED
Hi,I am trying to implement an ECO with conformal ECO but it doesn't use the spare cells list that I give.I am using the following commands:add_spare_cell -sparecell *spare* add_spare_cell...
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Conformal ECO use cell out of spare(NO_MAP)
When I use conformal ECO and read the log file, I found that eco logic uses out of spare and NO_MAP cell.Like below report:cs_sum_dis_reg NO_MAP...
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ComponentDefinitionProps documentation
Hello,I was looking for a piece of documentation about the fields that fall under ComponentDefinitionProps but wasn't able to find any. I had some problems the CLASS field at some point and I am...
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Genus: design elaboration : unusable library cells?
Hello,I've got strange messages when passing elaborate tcl command:Info : Found unusable library cells. [LBR-415] : Library: 'CORE65GPSVT_nom_1.00V_25C.lib', Total cells: 866, Unusable cells:...
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List of Highest Fanouts
Hello,Is there a way to create a report with the highest fanouts? let's say the top 10 fanouts from the whole design?Thanks
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stretching LOW pulse signal for extra 100ns
Hello, i have a logic output from a D-flipflop which generates a reset signal with variable pulse width. I want to stretch this LOW pulse width with an extra 100ns added to the original pulse width...
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Reuse of Schematics across different Projects
Hi All,I have 1 huge project(day X) which has different reference power supply designs.Now I start a new project and I require 1 specific reference power supply from X.What is the easist way to do...
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Mouse wheel and [i][o] button doesn't zoom
Hi,I recently encountered a probelm where scrolling with the mouse wheel and [i][o] button does not zoom in or out both in "Allegro orcad capture CIS 17.2.2016 " .When I scroll the mouse wheel or...
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