In Simvision, how do I change the waveform font size of the signal names?
Hi Cadence, I use simvision 20.09-s007 but my computer screen resolution is very high. As a result, the texts are too small. In ~/.simvision/Xdefaults I changed that number to 16, from 12. But the...
View ArticleStream in gds to virtuoso from directory other than where cds.lib exists
I am scripting gds streamin using 'strmin', which works fine so far.But, as it apparently doesn't have an option to specify where the cds.lib file is, I have to run it from the directory where the...
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Genus: Generated netlist doesn't define subckts
Dear all, I'm trying to perform an LVS check using Calibre between a layout that was generated by Innovus and the initial netlist generated by Genus. However, once I hit Run LVS on Calibre, it reports...
View ArticleRequest information on Tools
We are looking for suitable tools that could be used for RTL design, IP-XACT based integration (third party IP) and RTL design verification ( SV / UVM based methodology).Request to share details on...
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DRC Developers question
This document resolved my first query,Article (11638952) Title: How to output power and ground nets to GDSURL: support.cadence.com/.../ArticleAttachmentPortalbut now I have 20 power and 20 groundbelow...
View ArticleConformal LEC can't finish at analyze abort step. How do I proceed?
Hi Cadence & forumers, I am running a conformal LEC with a flattened netlist against RTL. The run hang for 5 days at the "analyze abort" step which is automatically launched by the compare. The...
View ArticleDetailed waveform dumping for selected waveform
I'm currently trying to explore the verilog simulation option in cadence.One thing that comes to my mind that if there exists a way in cadence workflow to dump selected register/wire's waveform during...
View ArticleUnable to open 64bit version of simvison
I am not able to open 64bit version of simvision using the following :simvision -64 -wav "path to wav"This throws the error " /lib64/libc.so.6: version `GLIBC_2.14' not found"I am only able to open it...
View ArticleHow to generate "Sheet" column in a pin report?
Hi everyone, Is there any method to generate "Sheet" column for a pin report like table below? The column "Name.Pin" & "Signal" can be generated easily, but I have no idea to generate the column of...
View ArticleHow to identify old Orcad Schematic entry version
Good morning,I dug up an old project from 2005 and I should open the schematic to check some things.This is the schematic of a XILINX XC95108-pq160 CPLD which the XILINX ISE 6.1 software then...
View Articlecopy paste circuit from one schematic design to another
Hi, have two designs and would like to copy paste one area of circuit from the old design to the new design, best way/approach and guidance please..
View ArticleMerge several worklibs
Hi,I find there is a similar question 10 years ago and the answer is out of date, so I come to ask again.I have compiled 2 different blocks in 2 different paths, using basic xrun -f xxxx.f, generated 2...
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Regarding the loading of waveform signals in the waveform windown using the...
Hello,I am trying to load some of the signals of the design saved in the signals.svwf to the waveform windown via the tcl file, I am using the following commands but nothing works, Can you please help...
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Error orprobe3086
I got "no simulation data for marker" for each A<B, A=B and A>B markers. Simulation output doesn't show these outputs but the inputs shown. How can I solve this error?
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how to tell conformal to ignore certain combination of input
hiHow can I tell the LEC tool to ignore a combination of Primary input bus in both Golden and revised.For example in both Golden and revised there is input [3:0] data_inI want LEC not to check the case...
View Articleremoving cdn_loop_breakers from netlist
I was trying to remove the cdn_loop_breaker cells from the netlist. When I tried the below 2 things, it removing the cdn_loop_breaker cells but while connecting the cdn_loop_breaker cell input to its...
View ArticleWant to use Transmission Gate in my design?
I want to use a transmission gate in my design, but it is not available as a standard cell for Genus RTL synthesis. How can I perform an analysis of area, power, and critical path delay that includes...
View ArticleUnmapped points
Hi , I am using conformal v23.2 for LEC checking b/w RTL and Netlist. I am getting so many not mapped points in both golden and revised designs and I didn't find any similar correspondence key point...
View Articleask some functions that we don't know if it exists
We have a big circuit having 12K gates totally and trying to show it in one page slide visually. But it is so hard for us to shrink it down from gate-level to module-level. Do you have any function...
View Articlewhich tools support Linting for early stages of Digital Design flow?
I am trying to understand the Linting process. I know that mainly JasperGold is the tool for this purpose. Though I think JasperGold is more suited for later stages of the design. As a RTL Design...
View ArticleAsking for a software suggestion.
Hi. I'm a very new learner on Cadence. I want to synthesis my logic design for the maximum, minimum and an average results of delay, power dissipation and area under varying multiple inputs of...
View ArticleUsing ChipWare (CW) Components in Quartus FPGA Builds?
Is there a way to use encrypted ChipWare (CW) components in a Quartus FPGA build flow?
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regrading abnormal working of xcelium simulator during wavefrom simulation
hellow cadence support team,i am facing an issue in xcelium simulator while simulating verilog code. when i try to run signal wavefrom it does nto working. it comes with pop op windows which says ""...
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signal (done) transition missing in (xcelium -simvision) during simulation...
Hello,I'm running a behavioral simulation of my Verilog design using both Xilinx Vivado and Cadence Xcelium/SimVision.In Vivado, I can clearly see a signal (indicating end-of-count/status) rising at a...
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